Modelling and Fabrication of Micro-SOFC Membrane Structure
Fabrication process of micro-SOFC membrane structure using the bulk micromachining of silicon technique with SiO2 and Si3N4 sacrificial layers is presented in this study. The process involves back side photolithography, magnetron sputtering of platinum thin films, thermal evaporation of YSZ electrolyte, deep reactive ion etching of silicon, and, finally, release of free-standing membrane using CF4/O2 plasma etching.
X-ray analysis shows the cubic phase of YSZ electrolyte and platinum electrodes. Modelling of normal stress distribution in the micro-SOFC structure with the Si3N4 sacrificial layer shows that at high temperatures the substrate expands less than the coating, causing tensile stresses in the substrate area next to the coating and compressive stresses in the coating, as the substrate material has a lower coefficient of thermal expansion than the layered Pt/YSZ/Pt coating.
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